As the size of transistors forming integrated circuits decreases, the number of transistors in a given circuit area increases. The ability to locate one particular transistor in a circuit to perform repairs, for example, becomes significantly more difficult with the number and submicron size of the transistors. A typical approach for locating a particular circuit feature, i.e., transistor, in a silicon device utilizes a scanning electron microscope (SEM) system. While the SEM provides a high resolution topography of a top surface of a silicon device, internal metal interconnect and structure images are not provided by the SEM. Additionally, the common use of a polyimide layer as a protective top layer of silicon devices further inhibits the ability of the SEM to provide useful information for inspecting a device.
In conjunction with the SEM, a CAD (computer aided design) navigation tool typically aids in locating a particular feature of a silicon device. By registering three visible features, such as corner markings used as align marks, on SEM images of the silicon device with equivalent features of a device layout representation in the CAD tool, a position in the silicon device can be located by selecting a corresponding location coordinate in the CAD tool. Usually, this is accomplished by interfacing the computer system running the CAD tool with a stage holding the silicon device and driving the stage to the selected coordinate. Unfortunately, as a mechanical device, limitations exist in the accuracy of stage movement, e.g., to an accuracy of about 3 micron (.mu.m). Of course, with feature sizes of the silicon device on the order of 0.25 .mu.m, a difference of 3 .mu.m will result in missing the desired feature completely.
A further limitation to using a CAD tool is the lack of availability of a layout for every possible circuit design. While an optical image can be taken for a given design to form an image of the structure and features of the design, the image must then be scanned into a computer system and registered with the corresponding SEM image of the silicon device. Such activities are considered too time-consuming and laborious to be a preferred practice.
Accordingly, a need exists for a navigation system that assists in more accurately locating particular features of multi-layer IC devices. The present invention addresses such a need.